1. Field of the Invention
This invention relates generally to semiconductor fabrication, and more particularly to integrated circuits incorporating transistors with improved junction capacitances, and to methods of fabricating the same.
2. Description of the Related Art
One variant of a basic conventional metal oxide semiconductor ("MOS") transistor consists of a gate electrode stack fabricated on a lightly doped semiconductor substrate. The gate stack consists of a gate dielectric layer and a gate electrode. A source region and a drain region are formed in the substrate beneath the gate dielectric layer and separated laterally to define a channel region. The gate electrode is designed to emit an electric field into the channel region. Changes in the electric field emitted by the gate electrode enable, or alternatively, disable the flow of current between the source and the drain. In many processes, the source/drain regions consist of a lightly doped drain ("LDD") and an overlapping heavier doped region.
Switching speed is a primary indicator of MOS device performance. The switching speed of MOS transistors is affected by a variety of mechanisms, such as the channel transit time, i.e., the time required for a charge to be transported across the channel. However, the predominant mechanism affecting device speed is the time required to charge and discharge the various capacitances that exist between device electrodes and between interconnecting lines and the substrate. At the circuit level, the propagation delays are frequently limited by the interconnection-line capacitances. At the device level, however, the gate delay is determined primarily by the channel transconductance, the MOS gate capacitance and the parasitic or junction capacitances between the source/drain regions and the body, that is, the substrate or the well in circuits utilizing doped wells. Reductions in any or all of these capacitance values can result in increases in the device switching speed.
The gate capacitance of a MOS transistor may be decreased by decreasing the gate area, although this decrease is offset somewhat by a corresponding necessary reduction in the thickness of the gate dielectric layer. However, one of the major parasitic capacitances affecting the switching speed of a typical MOS transistor is junction capacitance. Tailoring junction capacitance involves a careful balancing of competing design considerations. As a general rule, lower doping levels in the substrate or body translate into lower junction capacitances. Indeed, obtaining maximum circuit performance from a MOS device involves maximizing the drive current and minimizing junction capacitances and body effect, all of which favor lower doping concentrations in the device body. However, competing design considerations, such as optimizing packing density, favors raising the same doping concentrations to avoid punchthrough and to achieve high field thresholds.
Many conventional MOS transistor fabrication techniques incorporate implants to adjust the threshold voltage, V.sub.T of the transistor and to prevent punchthrough. These implants, of necessity, modify the doping characteristics of the channel region. A disadvantage associated with the conventional fabrication technique is that such implants modify the doping characteristics across the entire width and breadth of a given well. Thus, in an n-channel device fabricated in a p-well, V.sub.T and punchthrough implants raise the effective doping level of the p-well and thus increase the resulting junction capacitance.
One conventional method for attempting to position V.sub.T adjust and punchthrough prevention impurities in the channel region involves the fabrication of a photomask with an opening that is positioned only over the anticipated channel region. The difficulty with this method is that the photomask has proven difficult to accurately and reliably fabricate. The problem can be traced to the tight lateral dimensions involved, i.e., sub-1.0 micron, and to the uncertainty involved in how closely the patterned opening in the photomask will conform to the dimensions and positions of the subsequently formed gate electrode and dielectric spacers.
Another disadvantage associated with the conventional MOS transistor fabrication is the potential for increased junction capacitance with the fabrication of abrupt pn junctions. The source/drain regions of a MOS device are normally heavily doped to minimize their resistivities. In processes utilizing ion implantation, this heavy doping concentration is normally achieved by performing a relatively high dosage, low energy implant. In an n-channel device, this type of implant produces a relatively steep tail-off in the n+ doping concentration at the pn junction. This rather steep dopant gradient results in a relatively high junction capacitance.
One conventional technique for attempting to reduce the doping gradient in the vicinity of the pn junction involves performing an additional source/drain implant to a much greater depth than the LDD and heavier doped region source/drain implants. The difficulty associated with this method is the fact that the high energy necessary to achieve a sufficient depth for the implant gives rise to a correspondingly high potential for impurity ions to bore through the gate electrode, particularly polysilicon gate electrodes, and either corrupt the doping of the gate itself, or the underlying gate oxide and/or channel regions. This outcome is a consequence of the fact that this third and deep implant is performed following gate definition.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.